The present invention relates to a nonvolatile semiconductor storage device, and in particular, to a nonvolatile semiconductor storage device (flash memory) constructed such that an erase operation is executed block by block.
FIG. 1 is a circuit diagram of a prior art nonvolatile semiconductor storage device of the above type, and FIG. 2 is a sectional view showing the construction of one of memory cell transistors constituting the nonvolatile semiconductor storage device. In FIG. 2, reference numeral 21 denotes a p-type Si substrate, reference numerals 22 and 23 denote a source and a drain, respectively, both constructed of an n-type impurity diffusion layer, reference numeral 24 denotes a floating gate, and reference numeral 25 denotes a control gate.
Erase, write and read operations of the memory cell transistor will be described next.
ERASE OPERATION (WRITE OPERATION OF INITIAL VALUE DATA 0)
This operation is executed by applying a specified negative voltage (-9 V, for example) to the source 22 and the substrate 21 of the memory cell transistor (with the drain 23 being in a floating state) and a specified positive voltage (10 V, for example) to the control gate 25 to thereby form a high electric field directed from the floating gate 24 to the source 22 so that electrons are injected into the floating gate 24 by an FN (Fowler-Nordheim) current to finally achieve a threshold voltage of a specified value or higher (3 V or higher, for example) of the memory cell transistor.
WRITE OPERATION OF DATA 1
This operation is executed by applying a specified positive voltage (5 V, for example) to the drain 23 of the memory cell transistor, grounding the substrate 21 (with the source 22 being in a floating state) and applying a specified negative voltage (-9 , for example) to the control gate 25 to thereby form a high electric field directed from the drain 23 to the floating gate 24 so that electrons are extracted from the floating gate 24 to the drain 23 by means of the FN current to finally reduce the threshold value of the memory cell transistor to a specified value (1.5 V, for example).
WRITE OPERATION OF DATA 0
When writing data 0, the voltage to be applied to the drain 23 is set to the ground potential. In this case, the electric field between the floating gate 24 and the drain 23 becomes a low electric field, so that no FN current is generated. Therefore, no electron is extracted from the floating gate 24, and the threshold value is maintained at the specified value or higher (3 V or higher), i.e., the initial value data 0 is maintained.
READ OPERATION
The read operation is executed by applying a specified positive voltage (3 V, for example) to the control gate 25 of the memory cell transistor and a specified positive voltage (1 V, for example) to the drain 23, with the source 22 and the substrate 21 grounded, and detecting a drain current flowing in this stage.
Referring now to FIG. 1, reference symbols BK1, BK2, . . . denote memory cell array blocks each including a memory cell array constructed by arranging in a matrix form memory cell transistors MT each having the construction shown in FIG. 2, word lines WL (WL11, . . . , WL18, WL21, WL28, . . . ) each connecting with the control gates of the memory cell transistors of an identical row, and bit lines BL (BL1, BL2, . . . , BLn) each connecting with the drains of the memory cell transistors of an identical column, each bit line being common to the plurality of blocks BK1, BK2, . . . Further, the sources of the memory cell transistors are connected all together to a common source line SL.
In the above nonvolatile semiconductor storage device, the erase operation is executed block by block. It is a matter of course that two or more blocks can be simultaneously erased. For example, when executing the erase operation on the block BK1, a specified negative voltage (-9 V, for example) is applied to the substrate and the common source line SL, while a specified positive voltage (10 V, for example) is applied to all the word lines WL11, . . . , WL18 of the block BK1. At this time, the bit lines BL are all placed in the floating state. Also, the word lines of the non-erased blocks BK2, . . . are all placed in the floating state, or made to have a specified negative voltage (-9 V, for example). As a result, the erase operation is executed on all the memory cell transistors of the block BK1. When simultaneously executing the erase operation on another block, for example the block BK2, the specified positive voltage is applied to all the word lines WL21, . . . , WL28 of the block BK2, too.
The write operation is executed word line by word line. For example, when writing data 1, 0, 1, . . . , 0 to the memory cell transistors MT111, 112, 113, . . . , 11n, respectively, connected with the word line WL11 of the block BK1, the substrate is grounded, the common source line SL is placed in the floating state, a specified negative voltage (-9 V, for example) is applied to the selected word line WL11 (at this time, the other nonselected word lines WL12, . . . are given, for example, the ground potential), and applied voltages for the bit lines are set to BL1=5 V, BL2=0 V, BL3=5 V, . . . , BLn=0 V. Thus, the above data are written to the memory cell transistors. The writing of data to the memory cell transistors connected to the other word lines is done in the same manner.
The read operation is executed by grounding the substrate and the common source line SL while applying a specified positive voltage (3 V, for example) to a word line WL connected with a memory cell transistor MT to be read and applying a specified voltage (1 V, for example) to a bit line BL connected with the memory cell transistor MT to be read, so that a drain current is detected.
In an external storage application aimed at replacing a magnetic recording medium by a flash memory, it is important to achieve an erase unit of about 512 bytes equivalent to that of the magnetic recording medium. To reduce the size of the erase unit to as small as about 512 bytes in the NOR-type flash memory shown in FIG. 1, it is necessary to divide the memory cell transistors into small blocks in a direction in which the bit lines are extended. However, when such a construction is adopted, a multiplicity of blocks will be arranged on an identical bit line. This increases a maximum cumulative time T of drain disturbs from which one memory cell transistor suffers in a write operation (T=write time of a single cell.times.(number of blocks-1).times.number of word lines in one block.times.number of rewrite assurance times (up to 10.sup.5 times)) in proportion to the increase in number of blocks. Therefore, in order to realize a small size of the erase unit, it is necessary to remarkably improve a drain disturb tolerance of a non-selected cell in the write operation (i.e., a tolerance for the cumulative stresses placed on the non-selected cell due to the writing to the other cells connected to the identical bit line), in comparison with the regular flash memory having a large erase unit. This is because, if a sufficient tolerance for the drain disturbs is not provided, the stored data will be destroyed by the drain disturbs.
In order to solve such a technical problem, there has been proposed a DINOR (DIvided bit-line NOR) type flash memory in which the bit lines have a hierarchical structure with the provision of select gates between memory cell array blocks (H. ONODA et al., "A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY", IEDM, 1992).
The construction of the DINOR type flash memory is shown in FIG. 3.
This flash memory differs from the regular flash memory shown in FIG. 1 in that the bit lines of the former have a hierarchical structure constructed of sub-bit lines BL11, BL12, . . . , BL1n (block BK1), BL21, BL22, . . . , BL2n (block BK2), . . . provided for each block and main bit lines BLm1, BLm2, . . . , BLmn provided commonly to all the blocks, and in that select transistors ST (ST11, . . . , ST1n; ST21, . . . , ST2n, . . . ) are inserted between the sub-bit lines BL in each block and the main bit lines BLm. For example, when writing to the block BK1, an turn-on voltage is applied only to the gates of the select transistors ST11, ST1n between the main bit lines BLm1, . . . , BLmn and the sub-bit lines BL11, . . . , BLn of the block BK1, and a turn-off voltage is applied to the gates of the other select transistors. Further, with the substrate grounded and the common source line SL placed in the floating state, a specified negative voltage is applied to a selected word line and specified write voltages are applied to the respective main bit lines BLm. By this operation, the write operation is executed on the memory cell transistors located on the selected word line of the selected block.
FIG. 4 shows a cross sectional view taken along the bit line direction of the DINOR type flash memory shown in FIG. 3. Note that hatching for some parts is omitted from the figure for the sake of simplicity of the drawing. In the figure, reference numeral 51 denotes a p-type Si substrate, reference numeral 52 denotes a p-type well 52, and reference numeral 53 denotes a memory cell transistor which includes a source 531, a drain 531, a floating gate (a first polysilicon layer) 532, and a control gate (a second polysilicon layer) 533. Also, reference numeral 54 denotes a select transistor including a source 541, a drain 541 and a gate (the first polysilicon layer) 542, reference numeral 55 denotes a sub-bit line (a third polysilicon layer), reference numeral 56 denotes a main bit line (a first metal layer), and reference numeral 57 denotes a second metal layer wiring constituting a main word line connected with the word lines (sub-word lines) of the blocks.
According to this construction, in the write operation to a certain block, no write voltage is applied to the sub-bit lines, or drains, of the memory cell transistors of the other blocks. Therefore, the drain disturb to a certain cell in the write operation is remarkably reduced. Concretely speaking on the basis of the arrangement shown in FIG. 3 and FIG. 4, the drain disturb time for a certain cell on a sub-bit line in a block decreases to only a time which it takes to write to the other seven cells on the same sub-bit line in the block.
As described above, in this DINOR type flash memory, the select transistors are provided between the blocks so that the write voltage is applied only to the bit lines of a selected block at the write time. Therefore, there is an advantage that the cumulative time of the drain disturbs of each memory cell transistor is remarkably reduced. However, the additional provision of the select transistors increases the chip area of the flash memory. In addition, use of the third polysilicon layer as the wiring layer leads to an increase of the process steps for fabricating the memory, consequently increasing the chip cost.
The Japanese Patent Laid-open Publication No. HEI 8-153396 discloses another DINOR type flash memory wherein in a write stage, a negative voltage is applied to a substrate and a positive voltage is applied to non-selected word lines to reduce the drain disturbs in the write stage.
In this prior art DINOR type flash memory, however, because the negative voltage is applied to the whole substrate in the write stage, the negative voltage is applied even to a substrate portion having a selected block of memory cell transistors including those to be subjected to a write operation. In this case, therefore, there is a problem that the memory cell transistors in the selected block suffer an increased gate disturb.